Advances in consumer electronics are creating a need for high speed analog-to-digital converters in applications such as high definition television (HDTV), magnetic recording sampling detectors, medical imaging, and digital transmission links for telecommunications and cable networks. Many of these applications are implemented in CMOS (complementary metal oxide semiconductor) rather than the more expensive BiCMOS technology.
Flash analog-to-digital converters (ADC) have been employed to realize very high speed conversions. The analog input voltage is fed to 2.sup.N -1 comparators in parallel which are coupled to a resistor ladder producing a predetermined number of ascending reference voltages. The comparators generate a cyclic thermometer code according to the input voltage level as compared with the reference voltage levels. The cyclic thermometer code is then decoded to produce the digital output. Flash analog-to-digital converters are fast but need a large number of comparators which typically require large areas and have high power consumption. Further, the large number of comparators connected to the input voltage result in a large parasitic load at the input node. Such a large capacitive load limits the speed of the converter.
Accordingly, techniques have been sought to reduce the number of comparators needed in a flash analog-to-digital converter. Folding is an analog preprocessing step used to achieve this end. The number of comparators required is reduced by the degree of folding. FIG. 1 is a graphical representation of the folding concept for a 5-bit converter with a folding factor of four. Folders used to generate folded signals are typically implemented with cross-coupled differential pairs. Interpolating is another technique that may be combined with folding to generate intermediate folded signals to reduce the number of folders required to generate the same number of folded signals. FIGS. 2A and 2B provide a graphical representation of the interpolation concept.
Folding circuits in the past have been implemented in bipolar semiconductor technology and generate folded voltage signals. A CMOS current folding circuit implemented by a number of differential pairs have been proposed in Michael Flynn et al., CMOS Folding ADCs with Current-Mode Interpolation, IEEE International Solid-State Circuits Conference, Feb. 17, 1995; and Michael Flynn et al., CMOS Folding A/D Converters with Current-Mode Interpolation, IEEE Journal of Solid-State Circuits, Vol. 31, No. 9, September 1996 (both incorporated by reference and hereinafter referred to as "Flynn et al."). A current signal interpolating technique using current dividers is also proposed in Flynn et al. When the folding and interpolating techniques are both employed in an analog-to-digital converter the signal path becomes longer because of the added layers of circuitry. This may result in slowing down the converter. Further, the transistors in the current divider may need to be relatively large in size for device matching. With the use of large devices, the large capacitance associated therewith may further contribute to a slower circuit. To function at low supply voltage levels, this scheme may also require additional circuitry, such as current mirrors.